The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures for a semiconductor having multiple fin field effect transistors (finFETs) where epitaxially grown source and drain regions of the finFETs are separated from each other.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as fin field effect transistors (finFETs), are fabricated in and on a single wafer. FinFETs employ semiconductor fins to introduce on-wafer topography. The semiconductor fins are often formed as an array of semiconductor fins having a periodicity, or fin pitch, to minimize etch bias due to pattern factor, i.e., the fraction of the area of the semiconductor fins within a unit area. In this case, some of the semiconductor fins need to be made with a smaller fin pitch as the size of complementary metal-oxide-semiconductor (CMOS) devices become smaller. For example, consider a static random-access memory that includes closely spaced pFET and nFET pair. As the density increases, the possibility of shorting occurring during a late stage epitaxy step increases. Such a step could include, for example, an epitaxy step that allows for connection of a metal contact to one or more fins of the pFET and/or nFET. A method of avoiding such shorting would be well received in the industry.